Product Summary

The C0402C0G220J500NY is a Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger. The C0402C0G220J500NY changes state with the positive transition of Clock (1CP and 2CP). The C0402C0G220J500NY is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

Parametrics

C0402C0G220J500NY absolute maximum ratings: (1)DC Supply Voltage, VCC: -0.5V to 7V; (2)DC Input Diode Current, IIK For VI ＜-0.5V or VI ＞VCC + 0.5V: ±20mA; (3)DC Drain Current, per Output, IO For -0.5V ＜VO ＜VCC + 0.5V: ±25mA; (4)DC Output Diode Current, IOK For VO ＜-0.5V or VO ＞VCC + 0.5V: ±20mA; (5)DC Output Source or Sink Current per Output Pin, IO For VO＞ -0.5V or VO ＜VCC + 0.5V: ±25mA; (6)DC VCC or Ground Current, ICC: ±50mA.

Features

C0402C0G220J500NY features: (1)Asynchronous Set and Reset; (2)Schmitt Trigger Clock Inputs; (3)Typical Propagation Delay = 18ns at VCC = 5V, CL = 15pF, TA = 25℃; (4)Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25℃; (5)Fanout (Over Temperature Range) Standard Outputs: 10 LSTTL Loads; (6)Bus Driver Outputs: 15 LSTTL Loads; (7)Wide Operating Temperature Range: -55℃ to 125℃; (8)Balanced Propagation Delay and Transition Times; (9)Significant Power Reduction Compared to LSTTL Logic ICs; (10)HC Types: 2V to 6V Operation; (11)High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V.

Diagrams

C0402C0G220J500NY block diagram

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